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Conference papers
Test Sequence Generation From Formally Verified SysML Models
Abstract : Test generation has been acknowledged as a cost-prone activity reducing productivity and time to market. The expected benefits of Model Based Systems Engineering include automated generation of test sequences from models. The paper proposes verification solutions for the System Modeling Language (SysML). In particular, the paper shows how to link test generation to formal verification. The proposed algorithms are implemented by the free software TTool. Two case studies support discussion on conformance and interoperability testing, respectively.
Cited literature [25 references]
https://hal.telecom-paris.fr/hal-02337493
Contributor : Ludovic Apvrille <>
Submitted on : Tuesday, October 29, 2019 - 2:45:17 PM
Last modification on : Thursday, November 5, 2020 - 3:10:19 PM
Long-term archiving on: : Thursday, January 30, 2020 - 7:32:04 PM
Contributor : Ludovic Apvrille <>
Submitted on : Tuesday, October 29, 2019 - 2:45:17 PM
Last modification on : Thursday, November 5, 2020 - 3:10:19 PM
Long-term archiving on: : Thursday, January 30, 2020 - 7:32:04 PM
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